The present invention relate generally to a phase change memory device and an operating method thereof, and more particularly to a phase change memory device and an operating method thereof for outputting effective cell data by applying a reference current suitable for the characteristics of each cell of the memory.
A nonvolatile memory has a data processing speed similar to that of a volatile Random Access Memory (RAM), however, unlike a volatile RAM, a nonvolatile memory conserves a data even when no power is supplied to the memory, i.e., when the power is turned off. Examples of a nonvolatile memory include a magnetic memory and a phase change memory (PCM).
FIGS. 1a and 1b are diagrams showing a conventional phase change resistor (PCR) 4.
The PCR 4 comprises a phase change material (PCM) 2 inserted between an upper electrode 1 and a lower electrode 3. When a voltage and a current are applied to the conventional PCR 4, a high temperature is generated in the PCM 2 such that an electric conductive state of the PCR 4 changes depending on the resistance of the PCM 2.
The PCM 2 may comprise AgLnSbTe. The PCM 2 may also comprise chalcogenide having chalcogen elements (S, Se, Te) as a main ingredient, and specifically includes a germanium antimonic tellurium (Ge2Sb2Te5) consisting of Ge—Sb—Te.
FIGS. 2a and 2b are diagrams showing the principle operation of the conventional PCR 4.
As shown in FIG. 2a, the PCM 2 can be crystallized when a low current, i.e., a current less than a threshold value, flows into the PCR 4. As a result, the PCM 2 is crystallized and acts as a low resistance material.
As shown in FIG. 2b, the PCM 2 can be amorphized when a high current, i.e., a current higher than a threshold value, flows into the PCR 4. That is, the temperature of the PCM 2 is increased higher than the melting point of the PCM 2 when a high current flows into the PCR 4. As a result, the PCM 2 becomes amorphous and acts as a high resistance material.
In this way, the PCR 4 is configured to store a nonvolatile data corresponding to the two resistance states. Data “1” refers to a low resistance state of the PCR 4, and data “0” refers to a high resistance state of the PCR 4, and as such the data can be stored to have one of the two logic states.
FIG. 3 is a diagram showing a write operation of a conventional phase change resistant cell.
Heat is generated when a current flows through the upper electrode 1 and the lower electrode 3 of the PCR 4 for a given time. As a result, a state of the PCM 2 is changed to be either crystalline or amorphous depending on the temperature generated according to the current applied to the upper electrode 1 and the lower electrode 3.
A low temperature heating state occurs when a low current flows for a given time. As a result, the PCM 2 becomes crystalline and the PCR 4, which acts as a low resistor, is at a set state. On the other hand, a high temperature heating state occurs when a high current flows for a given time. As a result, the PCM 2 becomes amorphous and the PCR 4, which acts as a high resistor, is at a reset state. A difference between two phases is represented by a change in electric resistance.
As shown in FIG. 3, a low voltage is applied to the PCR 4 for a period of time in order to write the set state in a write mode. On the other hand, a high voltage is applied to the PCR 4 for a shorter period of time in order to write the reset state in the write mode.
FIG. 4 is a diagram showing a read current relationship of a conventional phase change memory device.
Each cell included in a plurality of cell arrays has a different read current distribution depending on process, element, and design conditions. That is, the distribution of a set current Iset and a reset current Ireset becomes broader based on a single reference current Iref.
If a characteristic group of each cell is divided into three regions A, B, C, the distribution of the set current Iset and the reset current Ireset is located at a different region. As a result, read currents are overlapped in some cells based on the single reference current Iref.
A fail condition may occur in some cells when the reset current Ireset is incorrectly distinguished from the set current Iset by the reference current Iref due to the overlap discussed above.